RapidIO IP Core Qsys Design Example Simulation Warning - RapidIO IP Core Qsys Design Example Simulation Warning Description When you simulate the RapidIO Qsys design example, warning messages display. These messages complain of a missing rio_sys_onchip_memory2_0.hex file. Resolution This issue has no impact on simulation. You can ignore these warning messages. To avoid this issue, copy the rio_sys_onchip_memory2_0.hex file from the rio_sys/simulation/submodules directory to the current working directory. This issue is fixed in version 13.1 of the RapidIO MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']