Why does the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP fail on Window* OS? - Why does the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP fail on Window* OS? Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP might fail. This problem only occurs on Windows* OS. This problem occurs because the location of quartus_py.exe file has changed but the IP still calls the file from the previous location. Resolution To work around this problem, copy the quartus_py.exe file from <Quartus installation path>\qcore\bin64\quartus_py.exe to <Quartus installation path>\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting QS-17812 novalue ['Memory Controllers'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 26.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']