Why are SSTL-12, HSTL-12, and HSUL-12 input buffers unable to interpret incoming data correctly for the Agilex™ 5 FPGA A5E065B ES device? - Why are SSTL-12, HSTL-12, and HSUL-12 input buffers unable to interpret incoming data correctly for the Agilex™ 5 FPGA A5E065B ES device? Description The reference voltage for the SSTL-12, HSTL-12, and HSUL-12 input buffers is incorrectly set to POD12 input level when operating in GPIO mode in the current Quartus® Prime software. Resolution The referenced voltage settings for SSTL-12, HSTL-12, and HSUL-12 inputs will be fixed starting from the Quartus® Prime software version 25.1 and above. Custom Fields values: ['novalue'] Troubleshooting 22020737287 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']