Logic elements utilization in FPGA - Logic elements utilization in FPGA Hello All, I have an old design on cyclone 3 with Quartus 10 and the used logic elements (in ALMs) are 20k. Now, I migrate exactly the same design to Quartus 21 also I changed the FPGA to Cyclone V and now the used logic elements (in ALMs) are 4k. So the only changes are the FPGA from Cyclone 3 to V and the Quartus version from 10 to 21. Why the used logic elements (in ALMs) reduced from 20k to 4k? What could wrong happend? w PS. no optimization is done for both Quartus project. Replies: Re: Logic elements utilization in FPGA Hi, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. If any answer from the community or Intel Support are helpful, feel free to rank your support experience by rating 4/5 survey. Please let me know of any inconvenience so that I may improve your future service experience. Have a great day! Best regards, Nurina Replies: Re: Logic elements utilization in FPGA Hello, Have you checked for the tri-state nodes as mentioned in the warnings? I'm not familiar with tri-state usage in Cyclone V, but here are some threads that you may find useful: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Warning-Tri-state-nodes-do-not-directly-drive-top-level-pins/td-p/213330#:~:text=FPGA%20devices%20don't%20support,not%20possible%20for%20internal%20nodes . https://community.intel.com/t5/Intel-Quartus-Prime-Software/An-important-warning-confused-me-tri-state-nodes-do-not-directly/td-p/180090 https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-tri-state-the-configuration-pins-after-configuration-with/td-p/731909 As for your PLL clock settings warning, here are some threads you may find useful. It just seems like there is issues with the constraints, I would suggest using derive_pll_clocks : https://community.intel.com/t5/Programmable-Devices/How-to-deal-with-this-warning/td-p/76741 https://www.intel.com/content/www/us/en/support/programmable/articles/000074876.html Regards, Nurina Replies: Re: Logic elements utilization in FPGA Hi, the basic point wasn't yet mentioned. Cyclone III (respectively IV or 10) LE is a completely different metric than Cyclone V ALM. Cyclone III LE has one 4-input LUT, ALM has two 6-input LUTs. Effectivity of 4- versus 6-input LUTs is different depending on the complexity of logic or arithmetic operations. Therefore it's difficult to define a general factor. Replies: Re: Logic elements utilization in FPGA Hello @Nurina , I got this after all the compilation complete(no error, or critical warning), I believe the design is good, but I want to double-check with you for the last time. Do You think it is fine? Thank you so much for your support. Replies: Re: Logic elements utilization in FPGA Hi Taha, Yes, with a large software jump I would expect differences in the project. Be it ALM usage or place & route or timing performance. This is because as the Quartus versions change the optimization algorithm also changes. I would suggest to also check for nodes that have been synthesized away. If your design is small enough, you can see it in the netlist viewers. It is easier to check in the warning messages too. Check for the below warning message "Warning (14320): Synthesized away node" Regards, Nurina Replies: Re: Logic elements utilization in FPGA Thank you for quick reply @Nurina . The total registers drop from 10k to 7k. I am still facing some issues with the testing however, I just want to know if I can consider this drop as normal. Sure later on with simulation and test i will get the correct answer. But for know, is this might be normal cuz we have 11 years gap between the Quartus version and the fpga used? Cheers, Taha Replies: Re: Logic elements utilization in FPGA I'm not entirely sure. Have you checked for any logic/register that have been synthesized away? Is the design working as expected in simulation and hardware tests? Regards, Nurina Replies: Re: Logic elements utilization in FPGA Hello @Nurina , So, 16k drop in logic element usage still can be considered normal? Cheers, Taha Replies: Re: Logic elements utilization in FPGA Hi, This can happen when you change device or Quartus versions. It could be that the device and Quartus version is better at optimizing this. Regards, Nurina