E-Tile TX/RX out clock constraint - E-Tile TX/RX out clock constraint Hi, I've defined a data rate in my E-Tile IP and I want to switch the data rate using the E-Tile Avalon reconfiguration interface by setting the internal PLL multiplier. Now I have chosen the highest data rate in E-Tile and want to constraint the lowest data rate. Do I have to set the constraint to the output clock of the E-Tiles? Which clock do I have to constraint here? I already tried a lot of combinations e.g.: create_clock -period 3.531 -name freq_low [get_ports {u0|e_tile_phy_0|e_tile_phy_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|out_pld_pcs_rx_clk_out1_dcm}] This statement won't be recognised but I can see the port in my tech-map. If I create a clock_group I can use [get_clocks {u0|e_tile_phy_*|e_tile_phy_*|rx_clkout|ch*}] but for create_clock I have to specify a port/pin/etc. instead of using an existing clock. How can I apply the create_clock constraint to my E-Tile out clocks for the lowest data rate? Best regards, Michael Replies: Re: E-Tile TX/RX out clock constraint Michael, Apologize for the late reply on this. You can try to refer to the following UG to find some of the E-Tile hard IP example designs which were validated by engineering. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-etile-hip-ethernet.pdf See if it is helpful. Replies: Re: E-Tile TX/RX out clock constraint Hi Michael, I'm checking for some user guide/sample design for reference how to constraint this. Will keep you posted. Replies: Re: E-Tile TX/RX out clock constraint Hi, is there anyone who could help me with this topic? I'm still not able to assign any create_clock constraint on the E-Tile TX/RX output clock to support different frequencies and data rates. Best regards, Michael Replies: Re: E-Tile TX/RX out clock constraint Hi Kenny, I'm using the Stratix 10 SM16BEU2 device. "What you need to do is create clock at the port and use derive_pll_clocks to generate the correct output clocks." Which port should have this create_clock constraint? I already tried a lot ports in the E-Tile native to constraint but without success. Best regards, Michael Replies: Re: E-Tile TX/RX out clock constraint Also, can you double check the user guide and reference design for the constrain needed? Replies: Re: E-Tile TX/RX out clock constraint What device that you were using? What you need to do is create clock at the port and use derive_pll_clocks to generate the correct output clocks. You can also open up timing analyzer to put the derive_pll_clocks inside the tcl command. It will show you a list of generated clock inside. Btw, if you want to change to different clock unit. Here is the command: set_time_format -unit ns -decimal_places 3