Introduction to Hyper-Retiming - 16 Minutes In the Introduction to Hyper-Retiming course, you will learn how to employ Hyper-Retiming, the first of three optimization steps to improving your design’s performance with the Altera® Hyperflex™ architecture, with each step allowing you to move you up the performance curve. This course will show you how Hyper-Retiming works and the advantages Hyper-Retiming has over traditional forms of retiming used in conventional FPGA architectures today. Course Objectives At course completion, you will be able to: Define how Hyper-Retiming differs from conventional retiming Describe how Hyper-Retiming works in Agilex™ and Stratix® 10 devices Skills Required Familiarity with FPGA/CPLD design flow Familiarity with Altera® Quartus Prime Pro design software Familiarity with Verilog or VHDL synthesizable design structures If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com. Reference Course Code: FPGA_OS10IHYPRET. FPGA_OS10IHYPRET. <p>Introduction to Hyper-Retiming</p>