I3C-T: MIPI I3C Basic Target - The I3C-T core is a flexible, target-only MIPI® I3C controller compliant with the latest I3C-BasicSM specification. Supporting SDR communication while tolerating HDR traffic, it interoperates with… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & compliant with the latest MIPI I3C-BasicSM specification. The highly featured target-only core communicates in Single Data Rate (SDR) mode, but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. The I3C-T needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic Targets. It can be assigned a Dynamic Address by the bus controller, or use its legacy I2C static address, it supports Hot Join and is capable of generating In-Band Interrupts when directed by the host to do so. CAST is a MIPI Alliance member Designed for easy integration, the I3C-T can operate in two different modes. Under normal mode, data from private I3C or legacy I2C write transfers are stored to a FIFO, and made available to the host via an APB subordinate interface. In a similar way, the host provides data to be used for private I3C or legacy I2C read transfers via the core’s APB subordinate interface. Alternatively, the core can operate in I3C-to-AHB bridging mode, where it autonomously converts private I3C or legacy I2C transfers to accesses on its AHB manager port using a simple yet configurable over-I3C protocol. Under the I3C-to-AHB bridging mode, the core needs no software assistance and provides the I3C-controller access to the local AHB bus, enabling remote monitoring, configuration, debug, or data exchange. The selection between normal and bridging operation modes is under software control via the core’s control register. The highly flexible core offers synthesis-time and run-time configuration options, which allow adapting its size and behavior to the application requirements. For example, the AHB-manager interface and the clock domains synchronizers can be removed at synthesis time to reduce the core’s silicon footprint. During run-time, the I3C private data and I2C traffic can be bridged to the core's AHB manager interface or transferred to and from the host via the core's APB subordinate interface. Also, parameters defining the CCCs processing (e.g. own-address, provisional ID, acknowledge for different type CCCs), the over-I3C protocol (i.e. number address bytes, max number of data bytes), and the AHB-manager port behavior (e.g AHB burst type & address wrapping) are all run-time configurable via the core’s registers. The I3C-T core adheres to the industry’s best coding and verification practices to ensure trouble-free implementation in ASIC or FPGA technologies. Technology mapping, constraining, and scan insertion are straight-forward, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, an asynchronous reset line per clock domain, and clean clock domain crossing modules Audio / Video Access Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical Test Transportation Wireless I3C-T: MIPI I3C Basic Target Key Features Up to 12.5 Mbit/s, SDR-Capable and HDR-Tolerant Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6tMAE What's Included Verilog/System Verilog, encrypted Verilog/System Verilog, or FPGA netlist Ordering Information I3C-T a1JUi0000049U6tMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-10-31T21:05:10.000+0000 The I3C-T core is a flexible, target-only MIPI® I3C controller compliant with the latest I3C-BasicSM specification. Supporting SDR communication while tolerating HDR traffic, it interoperates with legacy I2C devices and can optionally function as an I2C target. The core autonomously handles relevant Common Command Codes (CCCs), supports dynamic or static addressing, Hot-Join, and In-Band Interrupts. It offers two operating modes: normal mode, where data transfers use an APB subordinate interface, and I3C-to-AHB bridging mode, where private I3C/I2C transactions are automatically converted into AHB accesses for remote monitoring, configuration, debug, or data exchange without software intervention. With both synthesis-time and run-time configurability, the I3C-T adapts to application needs while minimizing footprint. Designed with best coding practices, clean clock domain crossings, and FPGA validation, it ensures reliable, low-risk integration. Partner Solutions