Why does the GTS JESD204B IP and GTS JESD204C IP with HVIO PLL clocking mode enabled failed the Quartus® Fitter compilation? - Why does the GTS JESD204B IP and GTS JESD204C IP with HVIO PLL clocking mode enabled failed the Quartus® Fitter compilation? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may observe the following error during Fitter compilation: "One or more blocks are configured incorrectly and will not have the desired functionality. --bcm instance name: hvio_1_1" This error occurs because Quartus® automatically assigns the hvio_refclk* port to an illegal location during placement. Resolution To work around this problem, you can manually assign the hvio_refclk* port to a HVIO bank. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 31020088213 novalue ['Interfaces JESD204B (Primary)', 'Interfaces JESD204C (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']