CAN-CTRL: CAN 2.0, CAN FD, & CAN XL Bus Controller Core - "The CAN-CTRL is a CAN bus controller compliant to Classical CAN, CAN FD, and CAN XL. The core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA The CAN-CTRL implements a highly featured and reliable CAN bus controller that performs serial communication according to the Controller Area Network (CAN) protocol. It supports classical CAN, CAN FD & CAN XL according to ISO 11898-1:2024; Time-Triggered CAN (TTCAN) per ISO 11898-4; and CAN Frame time-stamping as described in the CiA 603 profile. This CAN controller core handles data rates exceeding 20Mbit/s and it is optimized for the AUTOSAR and SAE J1939 specifications. The CAN-CTRL is especially efficient in minimizing host CPU overhead and simplifying software development. It automatically drops incoming messages using run-time programmable acceptance filters, so that unwanted messages never reach the host system. The core also enables flexible scheduling of outgoing messages with minimum software overhead. To this end, the core implements two transmit buffers: the primary transmit buffer (PTB) and the secondary transmit buffer (STB). The PTB is able to store one CAN frame while the number of stored frames inside the STB is configurable. The STB may operate either in FIFO mode or may do frame reordering based on the priority of the CAN frame ID. The PTB has always highest priority regardless of the frame ID. Furthermore, polling the status of the core is not necessary because an interrupt line—driven by runtime maskable sources—notifies the host about actionable events on the CAN data bus or in the CAN controller core. Designed for ease of integration, the CAN-CTRL is controlled by and exchanges data with the host system via a single memory-mapped slave interface. This memory-mapped interface can be either a generic 32-bit or 8-bit parallel interface, or optionally a 32-bit AMBA® APB, AHB-Lite, Wishbone, or Avalon-MM interface. Data can optionally be transferred to and from the core via dedicated 32-bit Avalon ST streaming interfaces. Using these dedicated streaming interfaces might be preferable in cases where messages are transferred to and from the system memory by an external DMA engine or when tight integration with a CANsec or other custom-hardware engine is required. To avoid limiting the host system, the host interfaces operate in an independent clock domain, which can be either synchronous or asynchronous to the core clock. Finally, to ease network operation, the core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error detection and analysis, bus diagnostics and optimization features Proven in hundreds of shipping products, certified by reputable testing houses, verified with third-party VIP, conformance-tested in plugfests, and developed to CAST’s stringent quality standards, the CAN-CTRL is likely the most reliable CAN controller IP core available. Communication Defense Industrial Medical Test Transportation CAN-CTRL: CAN 2.0, CAN FD, & CAN XL Bus Controller Core Key Features Supports Classical CAN, CAN-FD, CAN XL and TTCAN and is optimized for AUTOSAR and SAE J1939 Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6lMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information CAN-CTRL a1JUi0000049U6lMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-21T12:58:28.000+0000 "The CAN-CTRL is a CAN bus controller compliant to Classical CAN, CAN FD, and CAN XL. The core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). Finally, the CAN-CTRL provides error analysis, diagnosis, maintenance, and optimization features. The CAN-CTRL is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready. " Partner Solutions