What timing constraints are used by the Design Assistant? - What timing constraints are used by the Design Assistant? Description The Quartus® II Design Assistant (DA) does not use any constraints from the Synopsys Design Constraints ( .sdc ) file. During processing you may see the following messages: Info (332164): Evaluating HDL-embedded SDC commands Info (332104): Reading SDC File: '< file name >.sdc' These messages occur because the DA uses the timing netlist during processing. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']