Why is the E-Tile JESD204C Intel® FPGA IP bonded design example unreliable during link-up on hardware? - Why is the E-Tile JESD204C Intel® FPGA IP bonded design example unreliable during link-up on hardware? Description Due to an E-Tile transceiver PMA limitation, the E-Tile JESD204C Intel® FPGA IP bonded design example fails intermittently during link-up. Failure will cause either sync header lock (SH_LOCK) or extended multiblock lock (EMB_LOCK) at the receiver side to not be asserted. This problem is caused by an E-Tile PMA limitation where TX deskew misalignment occurs when channel bonding and double width transfer mode settings of the E-Tile Transceiver Native PHY IP in the E-Tile JESD204C Intel® FPGA IP are enabled. This problem can be observed using the E-Tile Transceiver Native PHY IP PMA Avalon® Memory-Mapped Interface at address 0x9h: cfg_tx_deskew_sts[2] (0x9 bit[4]) shows '0’ cfg_tx_deskew_sts[1:0] (0x9 bit[3:2]) shows NOT '11’ Resolution Due to the E-Tile transceiver PMA limitation, bonded mode option can no longer be supported. Starting in version 23.3 of the Intel® Quartus® Prime Pro Edition Software, only non-bonded modes will be supported. Custom Fields values: ['novalue'] Errata 15011481815 False ['JESD204C IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 21.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']