Why are there two different setup relationships for timing paths to the altera_reserved_tdo port in the TimeQuest Timing Analyzer? - Why are there two different setup relationships for timing paths to the altera_reserved_tdo port in the TimeQuest Timing Analyzer? Description Due to a problem in the Quartus® II software version 12.0 SP1 and later, you may see two different relationships for timing paths to the altera_reserved_tdo port. This problem occurs in Arria® V, Cyclone® V and Stratix® V designs that use the SignalTap™ II Logic Analyzer and manually constrain the altera_reserved_tdo port. The TimeQuest™ Timing Analyzer incorrectly reports timing paths from both the rising edge and the falling edge. Resolution This problem is fixed beginning with the Quartus II software version 12.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25