Why am I able to implement multiple independently enabled Open Drain I/O in the same x4 DQ group in 3V I/O banks in Intel® Stratix® 10 devices? - Why am I able to implement multiple independently enabled Open Drain I/O in the same x4 DQ group in 3V I/O banks in Intel® Stratix® 10 devices? Description In Intel® Stratix® 10 devices, each x4 DQ group in a 3V I/O bank shares the same Output Enable (OE) and therefore you cannot split the OE within a x4 DQ group. However, when you implement the following construct and place them in the same x4 DQ group: INOUT_1 < = ‘0’ when ENABLE_1 =’0’ else ‘Z’; INOUT_2 < = ‘0’ when ENABLE_2 =’0’ else ‘Z’; The Intel® Quartus® Prime Pro Edition Software will implement the I/O as Open Drain and modify the RTL by disconnecting the OE and move it to DATA IN . This will result in both I/O buffers having their OE port tied to GND , allowing them to be placed in the same nibble. Resolution This is an expected behavior. Custom Fields values: ['novalue'] Troubleshooting 18016740810 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']