Why are the feedback clock and the output clock misaligned in External Feedback and Zero Delay Buffer (ZDB) modes? - Why are the feedback clock and the output clock misaligned in External Feedback and Zero Delay Buffer (ZDB) modes? Description When external feedback mode or Zero Delay Buffer is selected as the compensation mode in Stratix® V, Arria® V, and Cyclone® V devices, the output clock will not have the expected phase relationship with the feedback clock. This is due to the Quartus® II software making incorrect delay chain settings in version 13.0 and earlier. Resolution If external feedback or ZDB modes are required, please submit a request to Altera technical support via mySupport. Custom Fields values: ['novalue'] Troubleshooting N/A False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 11.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']