IPM-BCH - For design that uses shorter packets and codes, a subset of our prevalidated and improved IPM-BCH is available to protect your private datas. IP-Maker was founded in 2010 by high throughput bus experts. IP-Maker is a young and dynamic team of senior electronic engineers who will help your company leverage on the latest technological… Arria® 10 GX FPGA Arria® 10 SX FPGA IP-Maker's powerful IPM-BCH is based on the BCH algorithm. The IP-Maker BCH Encoder/Decoder is full-featured with multiple parameters to fit your own needs in FPGA and SoC designs. In fact IPM-BCH Encoder/Decoder is fully configurable, allowing to it reach the best latency or the smallest footprint. Customizable parameters include: Chien Search algorithm, Galois Field, and data path. Flash Access Aerospace ASIC Proto Consumer Test IPM-BCH Key Features Customizable Data path Offering Brief No Yes No Yes Verilog Arria® 10 GX FPGA Arria® 10 SX FPGA No Yes 24.1.1 Offering Brief Production a1JUi000004YJKTMA4 What's Included IP core in source code customized for the need Ordering Information IPM-BCH 15000 Direct a1JUi000004YJKTMA4 Production Intellectual Property (IP) a1MUi00000BOWp7MAH a1MUi00000BOWp7MAH Member 2026-06-16T23:51:18.000+0000 For design that uses shorter packets and codes, a subset of our prevalidated and improved IPM-BCH is available to protect your private datas. Partner Solutions