Why doesn't the mmr_slave_readdatavalid signal de-assert when accessing the MMR ECC register? - Why doesn't the mmr_slave_readdatavalid signal de-assert when accessing the MMR ECC register? Description When you access the Intel Stratix® 10 or Intel Arria® 10 MMR ECC register, the mmr_slave_readdatavalid signal doesn't de-assert after being asserted. Resolution Open the <IP_generated_directory>\synth\altera_emif_io_hmc_ecc_mmr.v file and add the lines indicated by // NEW CODE (as shown below) for the 10'h080/10'h081/10'h082/10'h090/10'h091/10'h092/10'h093/10'h094 registers. 10'h080 : begin reg_clr_intr <= 1'b0; reg_clr_mr_rdata <= 1'b0; if (int_slave_write) begin reg_wrpath_pipeline_en <= slave_wr_data [ 10] & slave_byte_enable [1]; reg_ecc_code_overwrite <= slave_wr_data [ 9] & slave_byte_enable [1]; reg_enable_auto_corr <= slave_wr_data [ 8] & slave_byte_enable [1]; reg_enable_rmw <= slave_wr_data [ 2] & slave_byte_enable [0]; reg_enable_dm <= slave_wr_data [ 1] & slave_byte_enable [0]; reg_enable_ecc <= slave_wr_data [ 0] & slave_byte_enable [0]; end if (int_slave_read) begin int_slave_rd_data <= { {(CFG_MMR_DATA_WIDTH - 11){1'b0}}, reg_wrpath_pipeline_en , reg_ecc_code_overwrite , reg_enable_auto_corr , cfg_ecc_in_protocol , cfg_data_rate , reg_enable_rmw , reg_enable_dm , reg_enable_ecc }; int_slave_rd_data_valid <= 1'b1; end else // NEW CODE begin // NEW CODE int_slave_rd_data_valid <= 1'b0; // NEW CODE end // NEW CODE end This problem is scheduled to be fixed in a future release of the Intel Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting 491890 409839 True ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.0 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']