Reset Synchronizer for UniPHY External Memory Interfaces May Cause Design to Fail Timing when generated in SOPC Builder or Qsys - Reset Synchronizer for UniPHY External Memory Interfaces May Cause Design to Fail Timing when generated in SOPC Builder or Qsys Description Systems generated with SOPC Builder or Qsys may fail timing closure due to paths that include a reset synchronizer. Resolution A workaround for this issue is to apply the following constraint in the TimeQuest Timing Analyzer:For SOPC Builder: set_false_path -from {dut_sopc_top_reset_clk_0_domain_synch_module: dut_sopc_top_reset_clk_0_domain_synch*} For Qsys: set_false_path -from *:rst_controller*|*:alt_rst_sync_uq1| altera_reset_synchronizer_int_chain[*] -to *:controller_phy_inst| *:memphy_top_inst|*:umemphy|*:ureset|*:ureset_*_clk|reset_reg[*]. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']