Timing Closure Using Timing Analyzer Custom Reporting - 21 Minutes Learn how to use the Altera® Quartus® Prime Timing Closure Recommendations reporting in Timing Analyzer to help you find issues that may be causing timing failures. Course Objectives At course completion, you will be able to: use the timing closure Recommendation Custom reporting feature in timing Analyzer to close timing on your designs Identify HDL code changes needed to Address timing issues Change Altera® Quartus Prime software settings to Address timing issues Skills Required Background in digital logic design Basic understanding of Verilog HDL or VHDL coding an understanding of Basic FPGA design flow Basic understanding of the Altera® Quartus Prime user interface Basic understanding of timing Analyzer If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OTIM1100. FPGA_OTIM1100. <p>Timing Closure Using Timing Analyzer Custom Reporting</p>