When using the R-Tile Avalon® Streaming FPGA IP for PCI Express*, why is the number of completions different depending on which Hard IP port is being used? - When using the R-Tile Avalon® Streaming FPGA IP for PCI Express*, why is the number of completions different depending on which Hard IP port is being used? Description When using the R-Tile Avalon® Streaming FPGA IP for PCI Express*, the number of Completion Buffer Entries Required changes depending on which Port of the Hard IP is used due to the Width of the Completion Buffer for that port. Referring to R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide , 4.3.1.5.1. Completion Buffer Size, Table 61. Completion Buffer Size: When the IP is in x16 mode (Port 0), then the Completion Buffer Width is 512 bits or 64 bytes wide. When the IP is in x8 mode (Port 0 and Port 1), then the Completion Buffer Width is 256 bits or 32 bytes wide. When the IP is in x4 mode (Ports 0-3), then the Completion Buffer Width is 128 bits or 16 bytes wide. Resolution Referring to the examples given in Table 62. Completion Buffer Entries Examples: In the first example, the maximum number of Data Completion Buffer entries for Port 0(x16 Mode) is three because there are 3 data transfers of 64 bytes (worst case), and Port 0 supports a maximum of 64 bytes/transfer. For Port 1(x8x8 Mode), the number of Data Completion Buffer Entries needed is twice that of Port 0 because Port 1 can only support 32 bytes/request, so a total of 6 entries are required. For Ports 2/3(x4x4x4x4), the number of Data Completion Buffer Entries needed is twice that of Port 1 because Ports 2 and 3 can only support 16 bytes/request, so a total of 12 entries are required. #Note that with this example, the data transfer starts at an address on a 64-byte boundary. For the header, three Completion Buffer Entries are required for each port because the root port has an RCB value of 64, so it will take three requests of 64 bytes to complete the transfer of 192 bytes. In the second example described, the maximum number of Data Completion Buffer entries for Port 0 is still three because there are 3 data transfers of 64 bytes, and Port 0 supports a maximum of 64 bytes/transfer. Even though the Root port has an RCB value of 128, the endpoint can only process 64 bytes/request. For Port 1, the number of Data Completion Buffer Entries needed is twice that of Port 0 because Port 1 can only support 32 bytes/request, so a total of 6 entries are required. Again, for Ports 2 and 3, the number of entries doubles. #Note that once again, the data transfer starts at an address on a 64-byte boundary. For the header, two Completion Buffer Entries are required for each port because the root port has an RCB value of 128, so only two requests are needed to complete the transfer of 192 bytes. In the third example, the maximum number of Data Completion Buffer entries for Port 0 is four because of how the 64-byte data buffer is filled. The address starts on a 32-byte boundary instead of a 64-byte boundary. • The first transfer of 32 bytes is received and goes into buffer 0 • The first 32 bytes of the second transfer fill up buffer 0, and the last 32 bytes of the second transfer start filling up buffer 1. • The same thing happens with the third transfer, which fills up buffer 1 and the first half of buffer 2. • The same thing happens with the fourth transfer, which fills up buffer 2 and the first half of buffer 3. • The last transfer of 32 bytes then fills up buffer3 This results in a total of just 4 Complete Buffers needed for Port 0. As in the earlier examples, the number of entries will double for Port 1 and double again for Ports 2 and 3. For the header, five Completion Buffer Entries are required for each port because of the five separate transfer requests that are required to complete the transfer of 192 bytes. Custom Fields values: ['novalue'] Troubleshooting 13013557402 False ['R-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']