When using the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express with a 125MHz application clock frequency does the timing analyser report 250MHz being used? - When using the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express with a 125MHz application clock frequency does the timing analyser report 250MHz being used? Description Due to a problem in v20.3 the GUI for the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express, the GUI indicates support for 125MHz application clock frequency in Gen3 capable configurations of the IP. 125MHz application clock frequency is not supported, if selected the IP will be generated using a 250MHz application clock, no warnings, errors or informational messages will be seen. Resolution No workaround for this problem exists in v20.3 of the Intel® Quartus® Prime Pro Edition of software, as 125MHz is not supported. These incorrect 125MHz options have been corrected starting from version 20.4 of the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express IP. Custom Fields values: ['novalue'] Troubleshooting 14012524350 True ['Avalon-ST Stratix® 10 Hard IP for PCI Express', 'PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 20.3 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']