Where can I find the description of the test_out port? - Where can I find the description of the test_out port?
Description In the Stratix ® V Hard IP PCI Express user guide v12.0 page 15-6 you can find the test_out signal description. You can observer the lane0 and lane1 PIPE interface through test_out port. Resolution
Custom Fields values:
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Troubleshooting
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False
['PCI Express']
['FPGA Dev Tools Quartus II Software']
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11.0
['Stratix® V GX FPGA']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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