Why Agilex® 3 FPGA speed grade 7 design may fail timing when using Configuration Clock IP? - Why Agilex® 3 FPGA speed grade 7 design may fail timing when using Configuration Clock IP? Description In Quartus® Prime Pro Edition Software version 25.3.1 and prior, the Configuration Clock IP ( altera_s10_configuration_clock ) sets the internal oscillator clock frequency incorrectly for Agilex® 3 FPGA speed grade 7 devices. Agilex 3 FPGA speed grade 6 runs at 250 MHz while speed grade 7 runs at 200 MHz, but the IP configures both with a clock period of 4.000 ns (250 MHz) instead of the correct 5.000 ns (200 MHz) for speed grade 7. This may cause timing analysis failures in complex designs targeting Agilex 3 FPGA speed grade 7 devices. Simple designs may still pass timing. This problem does not affect Agilex 3 FPGA speed grade 6 devices. Resolution To work around this problem, manually edit the Configuration Clock IP SDC file before running compilation to change the internal oscillator clock period from 4.000 ns to 5.000 ns: 1. Open the Configuration Clock IP SDC file. 2. Locate the following line: create_clock -name altera_int_osc_clk -period 4.000 [get_nodes {*|intosc|oscillator_dut~oscillator_clock}] 3. Replace it with: create_clock -name altera_int_osc_clk -period 5.000 [get_nodes {*|intosc|oscillator_dut~oscillator_clock}] 4. Run compilation after applying the change. Note: If the design is regenerated in Platform Designer (Generate HDL), the SDC file will be overwritten with the incorrect value. The workaround must be reapplied after each regeneration. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15019122012 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 3 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']