When using the Low Latency Ethernet 10G MAC Intel® FPGA IP, why does the avalon_st_rx_pfc_pause_data signal de-assert for only one clock cycle after receiving an XON request in Priority-based Flow Control (PFC) implementation? - When using the Low Latency Ethernet 10G MAC Intel® FPGA IP, why does the avalon_st_rx_pfc_pause_data signal de-assert for only one clock cycle after receiving an XON request in Priority-based Flow Control (PFC) implementation? Description Due to a problem with the Intel® Quartus® Prime software version 18.0 and earlier, the Low Latency Ethernet 10G MAC Intel® FPGA IP's avalon_st_rx_pfc_pause_data signal is de-asserted for only one clock cycle after receiving an XON request in PFC implementations. The avalon_st_rx_pfc_pause_data signal continues to be asserted until the pause quanta expire or become zero. Resolution No workaround available. This problem has been fixed starting in the Intel® Quartus® Prime Pro version 18.1. Custom Fields values: ['novalue'] Troubleshooting FB: 590118; True ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.0 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']