How do I examine Intel® MAX® 10 FPGA on a Intel® Stratix®10 MX Development Kit? - How do I examine Intel® MAX® 10 FPGA on a Intel® Stratix®10 MX Development Kit? Description When Intel® Stratix® 10 MX FPGA is configured, examine for Intel® MAX® 10 FPGA may not work. Resolution Set SW2 of the Development Kit to the following settings prior to scanning the JTAG with the Intel® Quartus® Prime Programmer. This will enable user to access Intel® MAX® 10 FPGA reliably to examine the programmed data. Bit1: Open (OFF - On Board Intel® FPGA Download cable) Bit2: Open (OFF - Intel® MAX®10 JTAG IN) Bit3: Closed (ON - PCIe* Root Port JTAG OFF) Bit4: Closed (ON - Intel® Stratix® 10 MX JTAG OFF) This setting will remove Intel® Stratix ®10 from the JTAG, and examine will succeed. Custom Fields values: ['novalue'] Troubleshooting 1607833917 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.4 18.1 ['MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']