Why can I not enable 64B/66B block in Intel® Stratix® 10 L-tile or H-tile Native-PHY at 25.78125Gbps speed? - Why can I not enable 64B/66B block in Intel® Stratix® 10 L-tile or H-tile Native-PHY at 25.78125Gbps speed? Description Due to the speed limit of Enhanced PCS, the 64B/66B encoder and decoder can run up to 22.72 Gbps. Resolution There is no workaround. Custom Fields values: ['novalue'] Troubleshooting 1408205322 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.0 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']