Why are the rx_latency_adj and tx_latency_adj status signals for the 1588 enabled 1G/2.5G/5G/10G Multi-rate Ethernet PHY not stable upon reset? - Why are the rx_latency_adj and tx_latency_adj status signals for the 1588 enabled 1G/2.5G/5G/10G Multi-rate Ethernet PHY not stable upon reset? Description Due to the intellectual property (IP) behavior, you might that the observe rx_latency_adj and tx_latency_adj value are changing for a certain amount of iterations before they settle to a fixed value. Resolution No workaround is required. This is an expected behavior. The valid latency value is the fixed value after certain amount if iterations. The latency value changes after reset as it is statistically calculated, hence require certain amount of iterations before it settles to a fixed value. Custom Fields values: ['novalue'] Troubleshooting FB: 429504; False ['1G 2.5G 5G 10G Multi-rate Ethernet PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 16.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']