Why does the compilation report display 0.9V for the VCCL_HPS voltage regardless of the VCCL_HPS Value setting in Stratix® 10 SX device? - Why does the compilation report display 0.9V for the VCCL_HPS voltage regardless of the VCCL_HPS Value setting in Stratix® 10 SX device? Description Due to a problem in Quartus® Prime Pro Edition Software version 23.2 and earlier, the All Package Pins of the Compilation Report incorrectly display 0.9V for the voltage column for VCCL_HPS regardless of the VCCL_HPS Value setting in the Hard Processor System Stratix® 10 parameter settings. For example, even if you set VCCL_HPS Value to SmartVID, the All Package Pins of the Compilation Report incorrectly display 0.9V in the voltage column for VCCL_HPS. Resolution Ignore the VCCL_HPS voltage displayed in the All Package Pins of the Compilation Report in Intel® Stratix® 10 SX device. You can connect VCCL_HPS pins to 0.9V, 0.94V, or SmartVID selected in the Hard Processor System Intel® Stratix® 10 parameter settings. Custom Fields values: ['novalue'] Troubleshooting 14019671600 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 23.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']