FPGA Device Configuration Solutions - FPGA Device Configuration Solutions provides information for the various device configuration schemes and support documentation. FPGA configuration schemes and configuration support information. Design Pages {"title":"FPGA Device Configuration Solutions"} This device configuration support page provides resources for Altera® FPGA devices. Get additional support for Agilex™ 7 System Architecture , Agilex™ 5 System Architecture and Agilex™ 3 System Architecture , step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation. For other devices, search the Device and Product Support Collections . Device Configuration Schemes FPGA offers a wide range of configuration solutions to configure FPGA devices. Note that different FPGA devices support different configuration schemes. For general comparisons, go to the section on " Configuration Schemes Comparison ." FPGA Device Configuration Schemes Device Configuration Schemes Active Serial Active Parallel Passive Serial Fast Passive Parallel JTAG Configuration via Protocol (CvP) Hard Processor System (HPS) Avalon® Streaming Interface (Avalon-ST) (AS) x1 (AS) x4 (AP) (PS) (FPP) x8 (FPP) x16 (FPP) x32 x8/x16/x32 Agilex™ 7 - ✓ - - - - - ✓ ✓ ✓ ✓ Agilex™ 5 - ✓ - - - - - ✓ ✓ ✓ (Only supports up to by x16) Agilex™ 3 - ✓ - - - - - ✓ ✓ ✓ (Only supports up to by x16) Stratix® 10 - ✓ - - - - - ✓ ✓ ✓ ✓ Arria® 10 ✓ ✓ - ✓ ✓ ✓ ✓ ✓ ✓ ✓ - Cyclone® 10 GX ✓ ✓ - ✓ ✓ ✓ ✓ ✓ ✓ ✓ - Cyclone® 10 LP ✓ - - ✓ ✓ - - ✓ - - - MAX® 10 - - - - - - - ✓ - - - Stratix® V ✓ ✓ - ✓ ✓ ✓ ✓ ✓ ✓ - - Arria® V SoC ✓ ✓ - ✓ ✓ ✓ - ✓ - ✓ - Arria® V ✓ ✓ - ✓ ✓ ✓ - ✓ - - - Cyclone® V SoC ✓ ✓ - ✓ ✓ ✓ - ✓ ✓ ✓ - Cyclone® V ✓ ✓ - ✓ ✓ ✓ - ✓ ✓ - - Stratix® IV ✓ - - ✓ ✓ - - ✓ - - - Cyclone® IV E ✓ - ✓ ✓ ✓ - - ✓ - - - Cyclone® IV GX ✓ - - ✓ ✓ - - ✓ - - - Stratix® III ✓ - - ✓ ✓ - - ✓ - - - Cyclone® III ✓ - ✓ ✓ ✓ - - ✓ - - - Cyclone® III LS ✓ - - ✓ ✓ - - ✓ - - - Stratix® II and Stratix® II GX ✓ - - ✓ ✓ - - ✓ - - - Arria® II GX ✓ - - ✓ ✓ - - ✓ - - - Cyclone® II ✓ - - ✓ - - - ✓ - - - Stratix® and Stratix® GX - - - ✓ ✓ - - ✓ - - - Arria® GX ✓ - - ✓ ✓ - - ✓ - - - Cyclone® ✓ - - ✓ - - - ✓ - - - Configuration Schemes Comparison General Comparison for the Various Configuration Schemes (Active, Passive, JTAG) Active or Passive Configuration Scheme Configuration Scheme Serial or Parallel Configuration External Memory and/or Configuration Device 1 Width of DATA Bus (In Bits) Relative Configuration Time 2 Active AS Serial Serial configuration (EPCS) device 1 Moderate AS Serial Serial configuration (EPCQ) device 1,4 Moderate AP Parallel Supported common flash interface (CFI) parallel flash memory 16 Moderate Passive PS Serial MAX® series CPLDs, or processor with flash memory 1 Slow Serial Download cable 1 Slow FPP Parallel MAX® series CPLDs, or microprocessor with flash memory 8, 16, 32 Fast JTAG Serial MAX® series CPLDs, or microprocessor with flash memory 1 Slow Serial Download cable 1 Slow Avalon-ST Parallel MAX® series CPLDs, or microprocessor with flash memory 8, 16, 32 Fast Notes: Different devices using the same configuration scheme may support a different external controller and/or configuration device. Refer to the configuration chapter of the respective Altera® FPGA device for more information. Configuration time is presented as a relative comparison and serves only as a general guideline. Configuration time varies for different configuration schemes and depends on the configuration file size, configuration data width, frequency of the driving clock, and flash access time. In general, Altera® FPGA configuration schemes are categorized into active configuration schemes or passive configuration schemes. In the active configuration schemes, the device controls the configuration process and gets the configuration data from an external memory device. Active serial (AS) and active parallel (AP) are active configuration schemes. The memory device is a serial configuration (EPCQ) device for AS configuration and a supported parallel flash memory for AP configuration. In the passive configuration schemes, the configuration device controls the configuration process and supplies the configuration data. The configuration device can be an external intelligent host, such as a PC, a microprocessor, or a MAX® series CPLD. Passive serial (PS), fast passive parallel (FPP), and JTAG are passive configuration schemes. Active and Passive Configuration Schemes Avalon-ST Active Serial Configuration Active Parallel Configuration Passive Serial Configuration Fast Passive Parallel Configuration JTAG Configuration Description Avalon-ST is a passive configuration method that can be performed using an Altera® FPGA configuration device, or an intelligent host such as a microprocessor. Configuration data is transmitted as packets over a dedicated data path with supported data widths of 8,16, and 32 bits. This scheme supports rapid reconfiguration and high throughput, with transfer rates determined by the data width and system clock. The Active Serial (AS) configuration scheme is supported in the 1-bit data width (AS x1) or the 4 bit data width (AS x4). AS configuration can be performed using an Altera® FPGA serial configuration (EPCS) device or a quad-serial configuration (EPCQ) device. During AS configuration, the FPGA acts as the configuration host, and the EPCS or EPCQ device acts as the configuration agent. The FPGA outputs the clock on the DCLK pin and receives the configuration data from the EPCS or EPCQ device on the data pin(s). You can perform active parallel (AP) configuration using a supported common flash interface (CFI) parallel flash memory. During AP configuration, the FPGA device is the host, and the parallel flash memory is the agent. Configuration data is transferred to the FPGA device on the DATA[15:0] pins. This configuration data is synchronized to the DCLK input. Configuration data is transferred at a rate of 16 bits per clock cycle. The DCLK frequency driven out by the FPGA device during AP configuration is approximately 40 MHz. Passive serial (PS) configuration can be performed using an FPGA download cable, an Altera® FPGA configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Altera® FPGA device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle. The JTAG configuration scheme uses the IEEE Standard 1149.1 JTAG interface pins and supports the JAM Standard Test and Programming Language (STAPL) standard. Serial Vector File (SVF) is supported in Altera® FPGA devices using third-party programming tools. The devices are designed such that JTAG instructions have precedence over any device configuration mode. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. JTAG configuration can be performed using an FPGA download cable or an intelligent host, such as a microprocessor. Configuration Method Use a processor as an external host Use a MAX® series CPLD as an external host Using an EPCQ device Using an EPCS device Using a supported common flash interface (CFI) parallel flash memory Use a processor as an external host Use a MAX® series CPLD as an external host Use a processor as an external host External Memory Interface Handbook, Chapter 13 (p.489) - Fast Passive Parallel (FPP) Configuration Scheme Use a MAX® series CPLD as an external host Altera® FPGA Download Cables Using download cable to download configuration data or to program data during prototyping into the system during production. Altera® FPGA Download Cable User Guide Download Cables JRunner Portable software driver used to configure an FPGA via a JTAG interface. Works on a PC or embedded processors. ByteBlasterTM II or ByteBlasterMVTM download cable can be used. Source code available for porting to an embedded system or other platform. Jam STAPL player Offers in-system programming (ISP) via JTAG interface. Works on a PC or embedded processors. ByteBlaster II or ByteBlasterMV download cable can be used. Embedded Solution SRunner: An Embedded Solution for Serial Configuration Device Programming Portable software driver used to program EPCS devices via an AS interface. Works on a PC using a ByteBlaster™ II download cable. Source code available for porting to an embedded system or other platform. MicroBlaster™ Software Driver Portable software driver used to configure an FPGA via a PS interface Works on a PC using a ByteBlaster™ II or ByteBlasterMV™ download cable Source code available for porting to an embedded system or other platform MicroBlaster Embedded Version Please refer to the Implementing the MicroBlaster Configuration on the ColdFire Development Board white paper Source code available for porting to an embedded or other platform Configuring the MicroBlaster™ FPP Software Driver white paper Portable software driver used to configure an Altera® FPGA via an FPP interface. MicroBlaster FPP Software Driver (ZIP) is targeted for embedded fast passive parallel configuration. Application Note AN 370: Using the Serial Flash Loader with the Quartus® II Software An in-system programmability (ISP) solution used to program EPCS devices via a JTAG interface. AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus® II Software Method to use the FPGA's JTAG interface to perform in-system programming for the parallel flash memory device. User Guide Configuration User Guide ASMI Parallel FPGA IP Core User Guide This IP core provides access to the memory in the EPCS/EPCQ/EPCQ-L/EPCQ-A device through parallel data input and output ports. Parallel Flash Loader FPGA IP User Guide Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the FPGA Parallel Flash Loader FPGA IP User Guide Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the FPGA. Related Documentation EPCS64 Configuration Device Errata Sheet AN 521: Cyclone® III Active Parallel Remote System Upgrade Reference Design MAX® Series Configuration Controller Using Flash Memory White Paper Using a MAX® or MAX® II device as a configuration controller to configure Altera® FPGAs from flash memory Source code in Verilog and VHDL MAX® Series Configuration Controller Using Flash Memory White Paper Using a MAX® or MAX® II device as a configuration controller to configure Altera® FPGAs from flash memory. Flash Memory Configuration Controller Source Code Reference Design in Verilog and VHDL. Stratix® IV Device Handbook, Volume 1, Chapter 12: JTAG Boundary-Scan Testing IEEE 1149.1 (JTAG) Boundary-scan testing in Stratix® III Devices IEEE 1149.1 (JTAG) Boundary-scan testing in Stratix® II and Stratix II GX Devices IEEE 1149.1 (JTAG) Boundary-scan testing for Cyclone® III Devices IEEE 1149.1 (JTAG) Boundary-scan testing for Cyclone® II Devices IEEE 1149.1 (JTAG) Boundary-scan testing for Arria® GX Devices JTAG Boundary-scan testing for Arria® II Devices AN 39: IEEE 1149.1 (JTAG) Boundary-scan testing in FPGA Devices External Memory and/or Configuration Device All configuration schemes require either an external memory or a configuration device. These external devices are necessary to store configuration data and/or configure the Altera® FPGA when using a particular configuration scheme. For example, an external memory device can be a serial configuration (EPCQ) device or a supported parallel flash memory device. A configuration controller can be a microprocessor or any MAX® series CPLD. Note that different configuration schemes are supported by different external memories and/or configuration devices. The MAX® series CPLD supports Parallel Flash Loader intellectual property (IP) to program common flash interface (CFI) flash memory devices through the JTAG interface and provides the logic to control configuration (Passive Serial and Fast Passive Parallel) from the flash memory device to the FPGA. Parallel Flash Loader FPGA IP User Guide MAX® Series Configuration Controller Using Flash Memory White Paper Width of DATA Bus The width of the DATA bus determines the number of bits transmitted per DCLK cycle for the configuration scheme. In general, the configuration schemes can also be grouped in either serial configuration schemes or parallel configuration schemes. Serial configuration schemes transmit 1 bit per DCLK cycle. PS, AS, and JTAG are serial configuration schemes. On the other hand, parallel configuration schemes transmit more than 1 bit per DCLK cycle. The FPP configuration schemes transmit 8, 16, and 32 bits per DCLK cycle. The AP configuration scheme transmits 16 bits per DCLK cycle. Generally, the higher number of DATA bits transmitted per DCLK cycle contributes to a shorter configuration time. Relative Configuration Time The configuration cycle consists of three stages: reset, configuration, and initialization. The relative configuration times here refer only to the configuration stage. The time it takes for the device to enter user mode is actually longer. Configuration time varies for different configuration schemes and depends on the configuration file size, configuration data width, frequency of the driving clock, and flash access time. You can estimate the relative configuration time between various configuration schemes of the same device family and density. AS configuration time is dominated by the time it takes to transfer data from the EPCQ to the FPGA device. The AS interface is clocked by the FPGA DCLK output generated from an internal oscillator. The DCLK minimum frequency when using the 40 MHz oscillator is 20 MHz (50 ns). For example, the maximum AS configuration time estimate for an EP3C10 device is (2.5 Mb of uncompressed data) = RBF size x (maximum DCLK period / 1 bit per DCLK cycle) = 2.5 Mb x (50 ns / 1 bit) = 125 ms. In general, the FPP configuration schemes have the shortest configuration times. For all the FPP schemes, the configuration frequency is controlled by the external device. The AS, PS, and JTAG configuration schemes have a relatively slower configuration time. However, the relative configuration time is just an estimate. The actual configuration time depends heavily on the configuration data width, the configuration frequency at which the device is clocked, the configuration file size, and the flash access time. Support for CLKUSR Feature In some devices, the CLKUSR pin is an optional pin that inputs a user-supplied clock to synchronize the initialization of one or more devices after configuration. This feature allows one or more devices to enter user mode at the same time. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus® Prime or Quartus II software. Scalability The Altera® FPGA EPCS devices and EPCQ devices support a single-device configuration solution for Agilex® series, Stratix® series (except for Stratix® and Stratix® GX), Arria® series, and Cyclone® series FPGAs. To choose the appropriate configuration device, you must determine the total configuration space required for your target FPGA or chain of FPGAs. If you are configuring a chain of FPGAs, you must add the configuration file size for each FPGA to determine the total configuration space needed. Configuration via Protocol (CvP) Configuration via Protocol (CvP) is a configuration scheme that allows you to configure the FPGA fabric via the PCI Express (PCIe*) interface for various devices. The autonomous PCIe hard intellectual property (IP) allows the embedded PCIe core to operate before the FPGA is fully configured. This enables the FPGAs to easily meet the PCIe wake-up time requirement. Configuration via Protocol Support provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, Cyclone® 10, Stratix® V and Arria® V devices. Table 1. CvP Documentation and Resources Documentation Description Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide This document describes the CvP configuration scheme for Agilex™ 7 device family. Agilex™ 5 Configuration via Protocol (CvP) Implementation User Guide This document describes the CvP configuration scheme for Agilex™ 5 FPGAs. Agilex™ 3 Configuration via Protocol (CvP) Implementation User Guide This document describes the CvP configuration scheme for Agilex™ 3 FPGAs. Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide This document describes the CvP configuration scheme for Stratix® 10 device family. Arria® 10 CvP Initialization and Partial Reconfiguration Over PCI Express User Guide This user guide discusses the modes, topologies, features, design considerations, and software for CvP in 20 nm FPGAs. Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide This user guide discusses the modes, topologies, features, design considerations, and software for CvP. FPGA Configuration via Protocol White Paper This white paper describes how CvP helps your system meet the PCIe wake-up time requirement in 28 nm FPGAs. Table 2. CvP Drivers and Tools Driver and Tools Description Configuration via Protocol (CvP) - Upstream Open Source CvP Driver in Linux Systems (14 nm and 10 nm devices) The CvP driver support and download link to the driver can be found in the user guides below: Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Agilex™ 5 Device Configuration via Protocol (CvP) Implementation User Guide Agilex™ 3 Configuration via Protocol (CvP) Implementation User Guide Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide This is the code for an open-source Linux* driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system. Configuration via Protocol (CvP) - Software driver code (28 nm and 20 nm devices) Supported devices: Arria® 10 Cyclone® 10 GX Stratix® V Arria® V This is the code for an open-source Linux driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system. Reference Solutions Reference solutions to configure and program Altera® FPGA devices. Reference Solutions Serial Flash Loader In-system programming solution for Altera® FPGA serial configuration devices via a JTAG interface. AN 370: Using the Serial Flash Loader With the Quartus® II Software Parallel Flash Loader Used in MAX® II devices or Altera® FPGAs to program CFI flash memory devices through the JTAG interface and provides the logic to control configuration from the flash memory device to the FPGA. Parallel Flash Loader FPGA IP User Guide AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software MAX® Series Configuration Controller Using Flash Memory Using a MAX® or MAX® II device as a flash memory configuration controller to configure FPGAs MAX® Series Configuration Controller Using Flash Memory white paper Flash Memory Configuration Controller Reference Design (ZIP) MicroBlaster: Passive Serial or Fast Passive Parallel Configuration Portable software driver used to configure an FPGA via a passive serial (PS) or fast passive parallel (FPP) interface. Works on a PC using a ByteBlaster™ II or ByteBlasterMV™ download cable Configuring the MicroBlaster Fast Passive Parallel Software Driver white paper AN 423: Configuring the MicroBlaster Passive Serial Software Driver MicroBlaster Software Driver (ZIP) is available for embedded passive serial configuration. Jam STAPL: JTAG Configuration In-system programming solution to configure an FPGA via a JTAG interface. AN 425: Using Command-Line Jam STAPL Solution for Device Programming JRunner: JTAG Configuration Portable software driver used to configure an FPGA via a JTAG interface Works on a PC using a ByteBlaster II or ByteBlasterMV download cable AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration JRunner Software Driver (ZIP) available for porting to an embedded or other platform SRunner: EPCS Programming Portable software driver used to program EPCS devices via an active serial (AS) interface Works on a PC using a ByteBlaster II FPGA Download Cable AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming SRunner Software Driver (ZIP) available for porting to an embedded or other platform MorphIO: I/O Reconfiguration Configuration solution for any FPGA that supports an I/O reconfiguration feature. MorphIO: An I/O Reconfiguration Solution for FPGA Devices white paper MorphIO Tool (TCL) MorphIO software Readme file (TXT) Configuration Troubleshooters FPGA Configuration Troubleshooter Configuration Troubleshooters - 2026-03-10