Warning(332087): The master clock for this clock assignment could not be derived. Clock: *|core|arch_inst|c2p_fa_div_clk_** was not created. - Warning(332087): The master clock for this clock assignment could not be derived. Clock: *|core|arch_inst|c2p_fa_div_clk_** was not created. Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, the static timing constraints for the *c2p_fa_div_clk_** clock within the Agilex™ 5 LVDS SERDES IP may not be generated correctly. This problem occurs when the Agilex™ 5 LVDS SERDES IP is configured with more than 4 bytes in either the RX DPA-FIFO mode or RX soft CDR mode and implementing associated TX channels. Resolution To work around this problem. In the lvds_intel_lvds_core10_ph2_191_*.sdc file, replace: intel_lvds_create_generated_clock \ -source [intel_lvds_get_clock_source "$c2p_fa_gen_clk"] \ -divide_by 2 \ -duty_cycle 50 -phase 0 \ -name "${lvds_instance_name}|c2p_fa_div_clk_${byte}" -target "${c2p_fa_gen_clk}" with set master_clock "" set all_clocks [get_clocks -nowarn -of_objects [get_registers $c2p_fa_gen_clk]] foreach_in_collection clk $all_clocks { set clk_name [get_clock_info -name $clk] if {([string first $lvds_instance_name $clk_name] != -1) && ([string first "fclk0" $clk_name] != -1)} { set master_clock $clk_name break } } intel_lvds_create_generated_clock \ -source [intel_lvds_get_clock_source "$c2p_fa_gen_clk"] \ -divide_by 2 \ -duty_cycle 50 -phase 0 \ -name "${lvds_instance_name}|c2p_fa_div_clk_${byte}" -target "${c2p_fa_gen_clk}" \ -master_clock $master_clock This problem has been fixed in the Quartus® Prime Pro Edition Software version 23.4.1. Custom Fields values: ['novalue'] Troubleshooting 15014672982 False ['LVDS SERDES IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']