Simulation Fails with PLL Clocks Out of Synchronization for UniPHY External Memory Interfaces - Simulation Fails with PLL Clocks Out of Synchronization for UniPHY External Memory Interfaces Description During simulation, the PLL clocks lose synchronization. Resolution To work around this issue, follow these steps: In text editor open the design file and remove the following line: coverage exclude_file In the ALTPLL MegaWizard interface, turn on Create output files using the Advanced PLL parameters and regenerate the PLL (). Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL', 'Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']