LVDS SERDES - LVDS SERDES Hi, I have IP serdes in my FPGA (FPGA A) - This SERDES have connection with another FPGA (other board - FPGA B) According to my project requirements - I should inject(output) and get(input) clocks from FPGA A to FPGA B My question is : Should I place both clocks (in & out ) in the dedicated pin clocks or maybe I should do it only for the input clock ? Thanks Yishay Replies: Re: LVDS SERDES Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: LVDS SERDES I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users Replies: Re: LVDS SERDES Hello, Thanks for the details. Output clock at FPGA A can be placed at any LVDS pair pins and input clock at FPGA B should be sufficient. Thank you. Replies: Re: LVDS SERDES I drew a little VISIO that describe my design : My problem is : Unlock / Lock indication is depend by FPGA loading I wonder if the root cause is pin location - My question is : Should I place both clocks (in & out ) in the dedicated pin clocks or maybe I should do it only for the input clock ? Note : I dont have the option to locate input & output to SERDES pin dedicated clocks ( because board planning) Thanks Replies: Re: LVDS SERDES Hello, There is not enough information about your design but as far as I understand you can put both in and out in the dedicated pin. I'd advise you to check on both conditions you mentioned to see which one works. Thanks