Baseline JPEG Video Decoder IP Core - This compact, extremely efficient and low latency IP core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not… Advanced Logic Synthesis for Electronics (“A.L.S.E”), created in 1993, offers a complete range of IPs, Design Services, Trainings, and Boards to help you with the design of FPGA-based applications or… Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA Our Baseline JPEG Decoder (Decompression) IP core is capable of decoding standard JPEG-compressed images or Video on-the-fly and produce a raw video stream without any processor nor external memory. The latency is minimal. It is easily integrated in any design, with simple streaming interfaces. Can be used stand-alone or with Platform Designer. Video and Image Processing Aerospace Consumer Defense Industrial Baseline JPEG Video Decoder IP Core Key Features Low latency, standard, compact, no external memory, JPEG Decoder Offering Brief No No Yes No Encrypted Verilog Encrypted VHDL Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA No No Offering Brief Production Windows,Linux a1JUi0000049U4vMAE What's Included Depends on licensing scheme selected. Ordering Information JPEG-D a1JUi0000049U4vMAE Production Intellectual Property (IP) a1MUi00000BO8r0MAD a1MUi00000BO8r0MAD Select 2026-04-21T12:58:28.000+0000 This compact, extremely efficient and low latency IP core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not require any processor nor any external memory. Partner Solutions