Frequency of coreclkout Reported Incorrectly for Stratix V Hard IP for PCI Express IP Core when the ATX PLL is Used - Frequency of coreclkout Reported Incorrectly for Stratix V Hard IP for PCI Express IP Core when the ATX PLL is Used Description The frequency of coreclkout is reported incorrectly for the Stratix V Hard IP for PCI Express IP Core when the ATX PLL is used in Gen1 devices. The Quartus II software reports a frequency for coreclkout that is one half the actual frequency. Resolution The workaround is to add the following Synopsys Design Constraint (SDC) for coreclkout: create_clock -period <half of the Timequest-reported period> [get_pins {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}] For example, if TimeQuest reports a 16 ns clock, the SDC is: create_clock -period 8.000 [get_pins {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}] Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']