Why does the Avalon-MM DMA Hard IP for PCIe fail to return data for small DMA transfers? - Why does the Avalon-MM DMA Hard IP for PCIe fail to return data for small DMA transfers?
Description The Arria® 10 Hard IP for PCI Express with Avalon-MM DMA IP Core fails to return data for small DMA transfers. This problem can occur when the read size is less than 128bytes and the source address is aligned to 256bytes. Resolution This problem is fixed starting in the Quartus® Prime software version 16.1.
Custom Fields values:
['novalue']
Troubleshooting
FB: 372848;
False
['Arria® 10 Cyclone® 10 Hard IP for PCI Express']
['FPGA Dev Tools Quartus® Prime Software Pro']
16.1
16.0
['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document