Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of <clock frequency> on node gpll~PLL_OUTPUT_COUNTER' - Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of <clock frequency> on node gpll~PLL_OUTPUT_COUNTER' Description You may get this error in the Quartus® II software when the Device Speed Grade chosen in the Altera Phase-Locked Loop (Altera PLL) IP Core MegaCore® does not match the speed grade of your target Stratix® V, Arria® V or Cyclone® V device. Resolution Ensure the Device Speed Grade chosen in the Altera PLL IP Core MegaCore matches the speed grade of your target device. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['novalue'] novalue novalue ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']