RapidIO to AXI Bridge Controller (Silicon Proven IP for Altera Devices) - Mobiveil’s RIO-AXI Bridge provides a layered, configurable architecture connecting RapidIO to AXI-based systems. It includes high-speed DMA and streaming engines to meet demanding bandwidth needs… Mobiveil, Inc.(a GlobalLogic company) is a fast-growing technology company headquartered in Santa Clara, California, specializing in Silicon Intellectual Properties (SIP), application platforms, and… Arria® II GX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV GX FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Configurable RapidIO-to-AXI bridge IP that pairs with Mobiveil’s GRIO controller to expose a RapidIO host/device port on one side and AXI3/AXI4 on the system side, featuring multi-channel DMA, message and data-streaming modes, and robust error handling. RAB is a technology-independent, system-validated bridge that supports Serial or Parallel RapidIO, 1×/2×/4× lanes, and 64/128/256-bit internal datapaths with up to 256-byte payloads. It offers AXI PIO (configurable AXI slaves), RapidIO PIO (configurable AXI masters), multi-channel read/write DMA, and Message / Data-streaming / mixed operation. Control is via a PBUS register interface. Reliability features include hardware error recovery, exhaustive error reporting, pass-through for packets up to 288 bytes, and accept-all failover. Delivered with configurable RTL, HDL testbench, protocol checkers, bus watchers, performance monitors, and synthesis/verification guides. ASIC Proto Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Industrial Transportation 5G/ 6G Radio AI-RAN Baseband DAS/repeater/RIS NTN/Fixed Wireless RapidIO to AXI Bridge Controller (Silicon Proven IP for Altera Devices) Key Features Compliant with RapidlO specification, Revision 4.0 Offering Brief No Yes No No Encrypted Verilog Verilog Arria® II GX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV GX FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049UK0MAM What's Included Configurable RTL Code Ordering Information NA Direct a1JUi0000049UK0MAM Production Intellectual Property (IP) a1MUi00000BO8shMAD a1MUi00000BO8shMAD Select 2025-10-24T16:01:11.000+0000 Mobiveil’s RIO-AXI Bridge provides a layered, configurable architecture connecting RapidIO to AXI-based systems. It includes high-speed DMA and streaming engines to meet demanding bandwidth needs. Technology-agnostic and highly integrable, it suits cost-sensitive, performance-driven designs in FPGAs and ASICs. Partner Solutions