Error (175020): The Fitter cannot place logic pin in region (x, y) to (x, z), to which it is constrained, because there are no valid locations in the region for logic of this type. - Error (175020): The Fitter cannot place logic pin in region (x, y) to (x, z), to which it is constrained, because there are no valid locations in the region for logic of this type. Description This error might be observed in the Intel® Quartus® Prime Software when targeting Intel® Cyclone® 10 GX devices, and assigning LVDS I/O to 3V I/O banks. The LVDS I/O standard is not supported in 3V I/O banks in Intel® Cyclone® 10 GX devices. For additional information, refer to the Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook . Resolution None Custom Fields values: ['novalue'] Troubleshooting FB: 600004; 1408179877 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.1.1 ['Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']