Why does Aldec Riviera-PRO simulation fail/hang using the PHY Lite for Parallel Interfaces Intel® FPGA IP design example? - Why does Aldec Riviera-PRO simulation fail/hang using the PHY Lite for Parallel Interfaces Intel® FPGA IP design example? Description If PHY Lite for Parallel Interfaces Intel® FPGA IP design example is generated using the Intel® Quartus® Prime Pro Edition Software version 21.1 or 21.2, you will encounter the Aldec Riviera-Pro simulation hang or fail to simulate. This problem was root caused in the Aldec Riviera-Pro version 2020.04, which the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 generates simulation files for. Resolution This problem has been resolved in Aldec Riviera-PRO version 2021.4, which is supported in the Intel® Quartus® Prime Pro Edition Software version 21.3 and onwards. Regenerate your design with the updated Intel Quartus software version. Custom Fields values: ['novalue'] Troubleshooting 14012332298 False ['PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']