Current: xSPI Initiator core. - xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and… Synaptic Laboratories Ltd (SLL) are specialists in: (a) Design and supply of unified Multiple-Memory Bus Controller IP with extensive physical memory device qualification for a broad range of JEDEC… Cyclone® V E FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Synaptic Laboratories Ltd (SLL) supports well over 40+ xSPI (or xSPI-like) memory devices from all xSPI memory vendors, including: AP Memory, Everspin, GigaDevice, Infineon, ISSI, Macronix, Micron, Winbond, XC Memory. SLL supports all memory device variants on all major Altera FPGA device families. Consumer Data Center Cloud (Public, Private, Hybrid) Wireless Current: xSPI Initiator core. Key Features Support for all PSRAM, NOR Flash and STT-MRAM devices Offering Brief No Yes Yes Yes C/C++ Encrypted Verilog Cyclone® V E FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Yes No All xSPI memory devices from all vendors 25.1.0 Offering Brief Production Linux, Windows a1JUi0000049UOnMAM What's Included Encrypted IP Core, Documentation, Reference Project. Ordering Information SLL-xSPI-MBMC Direct a1JUi0000049UOnMAM Production Acceleration / AI / Cloud Intellectual Property (IP) a1MUi00000BO8tQMAT a1MUi00000BO8tQMAT Select 2025-10-08T20:23:02.000+0000 xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel. Partner Solutions