Why do I see an incorrect tx_outclock frequency when simulating the Altera Soft LVDS IP with MAX®10 devices? - Why do I see an incorrect tx_outclock frequency when simulating the Altera Soft LVDS IP with MAX®10 devices? Description Due to a known issue in Quartus® II software versions 14.1 and earlier, you may see an incorrect tx_outclock frequency when simulating the Altera® Soft LVDS IP with MAX® 10 devices. Resolution This known problem only affects simulation behaviour Custom Fields values: ['novalue'] Troubleshooting 1506810086 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 14.0 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']