Why do I see Linux prints multiple “unexpected MSI” messages in the PCIe Root Port with MSI design? - Why do I see Linux prints multiple “unexpected MSI” messages in the PCIe Root Port with MSI design? Description In a PCIe Root Port with an MSI design, the PCIe hard IP is connected to an MSI-GIC IP via a pipeline bridge. When Linux prints multiple “unexpected MSI” messages, you will observe unintended writes happen which do not belong to the MSI-GIC slave. Resolution A workaround is to add a second slave to the PCIe master next to the vector slave (MSI-GIC IP). This slave could be a small on-chip memory, a custom register, or something else. With a second slave and "Automate Default Salve Insertion" Interconnect feature enabled, MSI-GIC will not receive those unintended writes. Custom Fields values: ['novalue'] Troubleshooting 1507191529 False ['PCIe DMA Controller Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 19.3 16.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']