Why do I see JTAG problems when using the SignalTap II Logic Analyzer with the Quartus Prime Pro edition Sotware? - Why do I see JTAG problems when using the SignalTap II Logic Analyzer with the Quartus Prime Pro edition Sotware? Description In the Quartus® Prime Pro edition software, the JTAG signals are no longer automatically constrained by the software. As a result of this you may experience triggering problems using the SignalTap™ II Logic Analyzer and any other tools using the JTAG interface. Resolution Apply timing assignments, such as the examples below, to ensure correct functionality of the JTAG interface: set tck_freq 10MHz set tdi_input_delay_min 2 set tdi_input_delay_max 3 set tms_input_delay_min 2 set tms_input_delay_max 3 set tdo_output_delay_min 3 set tdo_output_delay_max 4 create_clock -name altera_reserved_tck -period [get_ports altera_reserved_tck] #cut all paths to and from altera_reserved_tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] # I/O min delays set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdi] -min set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tms] -min set_output_delay -clock altera_reserved_tck [get_ports altera_reserved_tdo] -min # I/O max delays set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdi] -max set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tms] -max set_output_delay -clock altera_reserved_tck [get_ports altera_reserved_tdo] -max Note that the values for tdi_input_delay_*, tms_input_delay_* & tdo_output_delay_* should match the destination hardware. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']