DisplayPort Arria V and Stratix V Design Examples Generate Cyclone V GXB Reset - DisplayPort Arria V and Stratix V Design Examples Generate Cyclone V GXB Reset Description The Arria V and Stratix V design examples in the DisplayPort IP core incorrectly generate the Transceiver Reset IP core in Cyclone V device. This issue does not affect the design. Resolution To work around this issue, edit the device family name in the gxb_reset.v file and regenerate the Transceiver Reset IP core. This issue will be fixed in version 15.1 Update 1 of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 15.1.1 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']