Hyperflex™ Architecture Design: Loop Optimization - 29 Minutes In the Hyperflex™ FPGA Architecture Design: Loop Optimization course, you will learn why design loops may produce timing bottlenecks in FPGA designs targeting devices built using the Hyperflex architecture, namely, Agilex™ series and Stratix® 10 FPGAs, what is meant by the term “critical chain” and how it relates to your design performance. You will learn about the common loops that appear in FPGA designs. While not all design loops cause performance limitations, by the end the class, you will have a few strategies that you can employ to optimize the loops that do. Course Objectives At course completion, you will be able to: Understand common loop structures found in FPGA designs Employ simple techniques to Reduce the impact of loops on performance Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Quartus® design software Familiarity with Verilog or VHDL synthesizable design structures If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHYPLOOP. FPGA_OHYPLOOP. <p>Altera Hyperflex FPGA Architecture Design: Loop Optimization</p>