Why is the o_rx_pfc port enabled for longer durations than expected with 10/25GE designs using the GTS Ethernet Hard IP with Priority Flow Control (PFC) enabled? - Why is the o_rx_pfc port enabled for longer durations than expected with 10/25GE designs using the GTS Ethernet Hard IP with Priority Flow Control (PFC) enabled? Description When operating the GTS Ethernet FPGA Hard IP for 10/25GE with PFC enabled, the o_rx_pfc port stays asserted beyond the configured quanta time whenever all of the following conditions are fulfilled: During the processing state of “PAUSE”, if new oversized frame is received Frame size larger than configured “maximum frame size” during the design generation in GTS Ethernet Hard IP. “Enforce maximum frame size” option is enabled in GTS Ethernet FPGA Hard IP GUI. The typical effect is an extended pause prior to resuming packet flow Resolution When enabled the “Forward RX pause requests” option in GTS Ethernet Hard IP GUI, disable the “enforce maximum frame size” option. There is no plan to fix this problem. Custom Fields values: ['novalue'] Troubleshooting 16028772378 novalue ['Interfaces Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 25.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']