Error: PLL Output Counter parameter 'phase_shift' is set to an illegal value - Error: PLL Output Counter parameter 'phase_shift' is set to an illegal value Description You might see this error when entering phase_shift values for output clocks in the Altera PLL megafunction in the Quartus® II software version 13.0: Error: PLL Output Counter parameter 'phase_shift' is set to an illegal value of '<phase_shift value> ps' on node '<node name>.' There is a bug in the Quartus® II software version 13.0 that can occur when you specify your PLL output counter phase_shift value in degrees in the Altera PLL megafunction. Resolution Open the Altera PLL megafunction and change your phase_shift value from degrees to ps. Custom Fields values: ['novalue'] Troubleshooting N/A False ['PLL'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']