Why is the simulation failing with a timeout error when running 1x10.3125G RSFEC Direct Mode (System PLL Clocking) Example Design of the GTS PMA/FEC Direct PHY IP using the Questa* – Altera® FPGA Edition simulator? - Why is the simulation failing with a timeout error when running 1x10.3125G RSFEC Direct Mode (System PLL Clocking) Example Design of the GTS PMA/FEC Direct PHY IP using the Questa* – Altera® FPGA Edition simulator? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, you may see simulation failure with a timeout error when running 1x10.3125G RSFEC Direct Mode (System PLL Clocking) Example Design of the GTS PMA/FEC Direct PHY IP using the Questa* – Altera® FPGA Edition simulator. This problem is limited only to 1x10.3125G RSFEC Direct Mode (System PLL Clocking). Example Design of the GTS PMA/FEC Direct PHY IP using the Questa* – Altera® FPGA Edition simulator. Resolution To work around this problem, modify the simulation timeout value defined in the file below. <design_example_dir>/example_testbench/rtl/param_defines.iv From: `define TIMEOUT 120000000 To: `define TIMEOUT 150000000 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 30020115989 False ['IP Examples'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1.1 ['Agilex™ 5 FPGAs and SoCs'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']