Is the Figure 55 of Credit Limit Update on Transmit Flow Control Credit Interface in the GTS AXI Streaming IP for PCI Express* User Guide correct? - Is the Figure 55 of Credit Limit Update on Transmit Flow Control Credit Interface in the GTS AXI Streaming IP for PCI Express* User Guide correct? Description In Figure 55 of the GTS AXI Streaming IP for PCI Express* User Guide version 24.3, you might see p<n>_ss_app_st_txcrdt_tdata[18:0] signal shows 'hFFF in cycle 9. The correct value for p<n>_ss_app_st_txcrdt_tdata[18:0] signal in cycle 9 is 'hFFFF. Resolution This information has been updated in the GTS AXI Streaming IP for PCI Express User Guide version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 15017194866 False ['F-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']