Does the ATX PLL to fPLL spacing requirement for transceiver L- and H-Tiles apply when using configuration profiles on Stratix® 10 devices? - Does the ATX PLL to fPLL spacing requirement for transceiver L- and H-Tiles apply when using configuration profiles on Stratix® 10 devices? Description Yes, the ATX PLL to fPLL spacing requirement for transceiver L- and H-tiles applies when using configuration profiles on Stratix® 10 devices. Resolution If your adjacent ATX PLL and FPLL components use the configuration profile feature to reconfigure to different datarates, you must manually check that the ATX PLL to fPLL spacing requirement is met for all configuration profile combinations. A critical warning is produced by the Quartus® Prime software when the default profile of the ATX PLL and fPLL violates the ATX PLL to fPLL spacing requirement. An example critical warning is below. Critical Warning(18499): FPLL <Gen_LHDx0.LHDx0|Gen_FPLL.Gen_FPLLUSR0.FPLL_i0|xcvr_fpll_s10_htile_0|fpll_inst > are too close to ATX PLL <Gen_LHDx1.LHDx1|Gen_ATXPLL.Gen_ATXUSR0.ATXPLL_i0|xcvr_atx_pll_s10_htile_0|ct1_atx_pll_inst>. FPLL with VCO frequencies within 50 MHz of adjacent ATX PLL must be separated by one FPLL. Modify the FPLL location constraints in the Assignment Editor to make fPLLs at least one ATX PLL apart. However, in the example below, no critical warning will be produced by the Quartus® Prime Software because the default profiles meet the VCO frequency rule for ATX PLL to fPLL spacing. The fPLL is constrained to location HSSICR2CMUFPLL_2T4DB Profile 0 = 10G3 (Default at compile time) Profile 1 = 12G5 The ATX PLL is constrained to location HSSICR2PMALCPLL_2T4DB Profile 0 = 10G3 Profile 1 = 12G5 (Default at compile time) The Intel® Stratix® 10 L- and H-Tile ATX PLL to fPLL spacing requirement is documented in the “3.1.1.1. ATX PLL to fPLL Spacing Requirements” section of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY IP user guide. Custom Fields values: ['novalue'] Troubleshooting 18010393365 True ['L-Tile H-Tile Transceiver ATX PLL Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 20.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']