Additive Latency Not Supported for HPS Hard Memory Controller in Arria V and Cyclone V SoC Devices - Additive Latency Not Supported for HPS Hard Memory Controller in Arria V and Cyclone V SoC Devices Description This problem affects DDR2, DDR3, and LPDDR2 products. Additive latency is not supported for interfaces targeting the HPS hard memory controller in Arria V or Cyclone V SoC HPS devices. Resolution There is no workaround for this issue. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']